HyperK Instruction Set Architecture Specification

Definitions

HyperK is defined to be expandable. Word length is at minimum 32-bits, but may also be any greater power of two. For now, only Hy32 and Hy64 are defined.¹

Register File

define reg { box wid 1.5 ht 0.2 $1 }
define pred { box wid 0.5 ht 0.2 $1 }
define label { $2 at 0.1 north of $1.nw; "0" at 0.1 north of $1.ne }
down
G0: reg("G0 (Zero)")
reg("G1 (Program Counter)")
reg("G2 (Loop Counter)")
reg("G3 (Stack Pointer)")
reg("G4")
reg("G5")
reg("G6")
reg("G7")
reg("G8")
G9: reg("G9")
L0: reg("L0/R10") with .w at 0.5 right of G0.e
reg("L1/R10")
reg("L2/R12")
reg("L3/R13")
reg("L4/R14")
reg("L5/R15")
reg("L6/R16")
reg("L7/R17")
reg("L8/R18")
reg("L9/R19")
reg("L10/R20")
reg("L11/R21")
reg("L12/R22")
reg("L13/R23")
reg("L14/R24")
reg("L15/R25")
reg("L16/R26")
reg("L17/R27")
reg("L18/R28")
reg("L19/R29")
reg("L20/R30")
L21: reg("L21/R31")
label(G0,"WLEN")
label(L0,"WLEN")
# line from G9.w left 0.3 then down until even with G0.w "Global" aligned above then to G0.w
# line from L21.e right 0.3 then down until even with L0.w "Local" aligned below then to L0.e
F0: reg("F0") with .w at 0.3 right of L0.e
reg("F1")
reg("F2")
reg("F3")
reg("F4")
reg("F5")
reg("F6")
reg("F7")
label(F0,"7")
P0: pred("P0 (False)") with .w at 0.3 right of F0.e
pred("P1 (True)")
pred("P2")
pred("P3")
pred("P4")
pred("P5")
pred("P6")
pred("P7")
pred("P8")
pred("P9")
P10: pred("P10") with .w at 0.3 right of P0.e
pred("P11")
pred("P12")
pred("P13")
pred("P14")
pred("P15")
pred("P16")
pred("P17")
pred("P18")
pred("P19")
pred("P20")
pred("P21")
pred("P22")
pred("P23")
pred("P24")
pred("P25")
pred("P26")
pred("P27")
pred("P28")
pred("P29")
pred("P30")
pred("P31")
label(P0,"1")
label(P10,"1")

Format Registers

HyperK has 8 format registers, which specify the format of operands. Each format register (F0-F7) is 8-bits wide. Its least significant bit specifies endianness, and the 7 most significant bits indicate bit field length. Attempting to invoke a format register with a bitfield length longer than WLEN will raise the INVALID_FORMAT fault. The length of the bitfield of the length field plus one. Pattern zero is reserved.²

Register Windowing

HyperK has a windowed register file. It also uses this same mechanism for SIMD: subroutines may allocate jumbo frames, as permitted by the underlying register set. This allows for scalar code to use the same resources for deep subroutine nesting (without having to invoke spill code).

Some amount of registers can be reserved for interrupt processing. This ensures that executing the WIN instruction within an ISR will never cause the SPILL fault, provided the window reserved is no larger than that reserved.

Encoding

HyperK is an intrinsically variable-length instruction set. Instructions are made up of 16-bit syllables. Instruction are always a multiple of 16-bits in length, and the total length of an instruction can always be determined entirely from the first syllable.

Set the number of registers reserved for interrupt processing

Instruction Formats

Short

• SF-Type
• SX-Type

Long

• LR-Type
• LI-Type

Extended

• XR-Type
• XI-Type

Addressing Modes

define bits { box wid 0.15 * $1 ht 0.2 $2 }
bits(5,"dest")
bits(5,"off")
bits(2,"scale")

Immediate

HyperK has several forms of immediates. Immediate mode is encoded in the opcode, not as an addressing mode, so as to not encode redundant forms (i.e. there is no need to ever perform arithmetic on two immediates).

Register Direct

The operand is contained within a register

Register Indirect

The operand is at the memory addressing pointed to by the register

Auto-increment

Auto-decrement

Instruction Set

Allocate Register Window - WIN

Move Address - ADR

Add Unsigned - ADDU

Add Signed - ADDS

Subtract Unsigned - SUBU

Subtract Signed - SUBS

Multiply Unsigned - MULU

Multiply Signed - MULS

Multiply Mixed Sign - MULM

Minimum Unsigned - MINU

Minimum Signed - MINS

Maximum Unsigned - MAXU

Maximum Signed - MAXS

Bitwise And - AND

Bitwise Inclusive Or - IOR

Bitwise Exclusive Or - XOR

Bit Shift - BSH

Arithmetic Shift - ASH

Rotate - ROT

Initiate Zero Overhead Loop - LOOP

Convert - CVT

This operation takes two format fields, which encodes the source and destination

Execute - EXE

S/360, PDP-10 style execute op, unsure on this one.

1. ^{^} I have considered, but rejected the possibility of Hy16 because the address space, a mere 8 KiB, is arguably too small to be useful. However, if there is interest, this could be revised. Non-power-of-two word lengths are also theoretically possible, but might pose issues for intra-register addressing modes.
2. ^{^} Operations over single bits are encoded as different operations, even where they logically coincide, like logical bitwise operations, because many/most arithmetic operations cease to be meaningful in the case of a single bit, and because the predicate registers are stored separately